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FPGA U1
1. Install the parallel port JTAG programming cable XILINX
Model Number DLC5, Parallel Cable III from the
computer parallel port to the ISL5239EVAL1 connector
J9 as follows:
? TMS to J9-7
? TCK to J9-9
? TDI to J9-16
? TDO to J9-18
? VCC to J9-19
? GND to J9-20.
2. Launch the Xilinx Device Programming iMPACT software
or any similar device programming software.
3. Select ‘File’ and then ‘Initialize Chain.’
4. This will identify the device and pop-up a file selection
window. Navigate to the desired .mcs file. In the ‘Select
Prom Part Name’ dialog box, select ‘xc18v01_vq44,’ and
then ‘OK’. This will allow the JTAG Programmer to display
the TDI - device - TDO chain, specifying the .mcs file as
5. Highlight the XC18v01 with the cursor, right click, and
select ‘Program.’ In the ‘Program Options’ dialog box,
check ‘Erase Before Programming’ and ‘Program’, then
‘OK’.
6. Verify all programming actions are completed
successfully. Troubleshoot the J9 JTAG to U3 path if
programming is unsuccessful.
7. Select File, then Exit to complete the programming
operations.
8. Remove power from the CCA.
9. Remove the serial port programming cable from
connector J9.
Eval Board Timing
The CPLD and FPGA load files constrain the devices to
particular timing parameters which are a function of the
configuration. The timing for the supplied CPLD is as
constrained in the programming files and as shown in Table
4. Additional timing information can be obtained by review of
the design utilizing Xilinx ISE or other CPLD programming
tools.
the programing file.
TABLE 4. CPLD Timing
Parameter
EXTERNAL CLOCK IN (J2)Frequency
EXTERNAL CLOCK IN (J2)Period
EXTERNAL CLOCK IN (J2) duty cycle @ 125 MHz
Delay from REF CLOCK OUT (J3) to CLOCK OUT (J10-19)
Symbol
FCLK
TCLK
Min
-
8.0
50% - 200
Max
125
-
50% + 200
7.0
Units
MHz
nS
pS
nS
in x1 mode
Delay from REF CLOCK OUT (J3) to CLOCK OUT (J10-19)
in x2, x4, or x8 mode
Setup Time from IDATA IN<17:0> (J10) to REF CLOCK
OUT (J3)
Hold Time to IDATA IN<17:0> (J10) from REF CLOCK OUT
(J3)
Setup time from QDATA IN<17:0> (J11) to REF CLOCK
OUT (J3)
Hold Time to QDATA IN<17:0> (J11) from REF CLOCK
OUT (J3)
REF CLOCK OUT falling edge (J3) to IDATA OUT<18:0>
(J1) Delay
REF CLOCK OUT falling edge (J3) to QDATA OUT<18:0>
(J5) Delay
EXT FEEDBACK IN<19:0> (J8) to EXT FDBCK CLK (J8-19)
Setup Time
EXT FEEDBACK IN<19:0> (J8) from EXT FDBCK CLK (J8-
19) Hold Time
2.0
2.0
2.0
2.0
2.0
2.0
8.0
4.0
4.0
nS
nS
nS
nS
nS
nS
nS
nS
nS
Internal vs. External Clock Drive
The ISL5239 is supplied with an on-board 125 MHz
oscillator in position U6. The board can also utilize an
external clock source through connector J2. Jumper J4
6
provides for the selection of either clock source, with the
default position J4 2-3 selecting the on-board U6 oscillator.
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